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700 MHz to 1000 MHz RF Vector Modulator AD8340
FEATURES
Cartesian amplitude and phase modulation 700 MHz to 1.0 GHz frequency range Continuous magnitude control of -2 dB to -32 dB Continuous phase control of 0 to 360 Output third-order intercept 24 dBm Output 1 dB compression point 11 dBm Output noise floor -149 dBm/Hz @ full gain Adjustable modulation bandwidth up to 230 MHz Fast output power disable 4.75 V to 5.25 V single-supply voltage
FUNCTIONAL BLOCK DIAGRAM
VPRF QBBP OBBM VPS2
90 RFIP RFIM 0
04699-0-001
RFOP RFOM
CMOP
IBBP IBBM
DSOP
Figure 1.
APPLICATIONS
RF PA linearization/RF predistortion Amplitude and phase modulation Variable attenuators and phase shifters CDMA2000, GSM/EDGE linear power amplifiers Smart antennas
GENERAL DESCRIPTION
The AD8340 vector modulator performs arbitrary amplitude and phase modulation of an RF signal. Since the RF signal path is linear, the original modulation is preserved. This part can be used as a general-purpose RF modulator, a variable attenuator/phase shifter, or a remodulator. The amplitude can be controlled from a maximum of -2 dB to less than -32 dB, and the phase can be shifted continuously over the entire 360 range. For maximum gain, the AD8340 delivers an OP1dB of 11 dBm, an OIP3 of 24 dBm, and an output noise floor of -149 dBm/Hz, independent of phase. It operates over a frequency range of 700 MHz to 1.0 GHz. The baseband inputs in Cartesian I and Q format control the amplitude and phase modulation imposed on the RF input signal. Both I and Q inputs are dc-coupled with a 500 mV differential full-scale range. The maximum modulation bandwidth is 230 MHz, which can be reduced by adding external capacitors to limit the noise bandwidth on the control lines. Both the RF inputs and outputs can be used differentially or single-ended and must be ac-coupled. The RF input and output impedances are nominally 50 over the operating frequency range. The DSOP pin allows the output stage to be disabled quickly in order to protect subsequent stages from overdrive. The AD8340 operates off supply voltages from 4.75 V to 5.25 V while consuming approximately 130 mA. The AD8340 is fabricated on Analog Devices' proprietary, high performance 25 GHz SOI complementary bipolar IC process. It is available in a 24-lead Pb-free LFCSP package and operates over a -40C to +85C temperature range. Evaluation boards are available.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
AD8340 TABLE OF CONTENTS
Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 4 ESD Caution.................................................................................. 4 Pin Configuration and Function Descriptions............................. 5 Typical Performance Characteristics ............................................. 6 Theory of Operation ...................................................................... 10 RF Quadrature Generator ......................................................... 10 I-Q Attenuators and Baseband Amplifiers.............................. 11 Output Amplifier ........................................................................ 11 Noise and Distortion.................................................................. 11 Gain and Phase Accuracy.......................................................... 11 RF Frequency Range .................................................................. 11 Applications..................................................................................... 12 Using the AD8340 ...................................................................... 12 RF Input and Matching ............................................................. 12 RF Output and Matching .......................................................... 13 Driving the I-Q Baseband Controls......................................... 13 Interfacing to High Speed DACs.............................................. 14 CDMA2000 Application............................................................ 14 Evaluation Board ............................................................................ 16 Outline Dimensions ....................................................................... 20 Ordering Guide .......................................................................... 20
REVISION HISTORY
6/04--Revision 0: Initial Version
Rev. 0 | Page 2 of 20
AD8340 SPECIFICATIONS
VS = 5 V, TA = 25C, ZO = 50 , f = 880 MHz, single-ended, ac-coupled source drive to RFIP through 5.6 nH series inductor, RFIM ac-coupled through 5.6 nH series inductor to common, differential-to-single-ended conversion at output using 1:1 balun. Table 1.
Parameter OVERALL FUNCTION Frequency Range Maximum Gain Minimum Gain Gain Control Range Phase Control Range Gain Flatness Group Delay Flatness RF INPUT STAGE Input Return Loss CARTESIAN CONTROL INTERFACE (I & Q) Gain Scaling Modulation Bandwidth Second Harmonic Distortion Third Harmonic Distortion Step Response Conditions Min 700 Maximum gain setpoint for all phase setpoints VBBI = VBBQ = 0 V Relative to maximum gain Over 30 dB control range Over any 60 MHz bandwidth Over any 60 MHz bandwidth RFIM, RFIP (Pins 21 and 22) From RFIP to CMRF (with 5.6 nH series inductors) IBBP, IBBM, QBBP, QBBM (Pins 16, 15, 3, 4) 250 mV p-p sinusoidal baseband input single-ended 250 mV p-p, 1 MHz, sinusoidal baseband input differential 250 mV p-p, 1 MHz, sinusoidal baseband input differential For gain setpoint from 0.1 to 0.9 (VBBP = 0.5 V, VBBM = 0.55 V to 0.95 V) For gain setpoint from 0.9 to 0.1 (VBBP = 0.5 V, VBBM = 0.95 V to 0.55 V) RFOP, RFOM (Pins 9, 10) Measured through balun Maximum gain setpoint Maximum gain setpoint, no input PIN = 0 dBm, frequency offset = 20 MHz f1 = 880 MHz, f2 = 877.5 MHz, maximum gain setpoint IS-95, single carrier, POUT = 0 dBm, maximum gain, phase setpoint = 45 Maximum gain VPS2 (Pin 5, 6, 14); RFOP, RFOM (Pins 9, 10) Includes load current DSOP (Pin 13) DSOP = 5 V Delay following high-to-low transition until device meets full specifications Delay following low-to-high transition until device produces full attenuation 4.75 110 -2 -32 30 360 0.25 10 20 2 230 47 45 45 47 Typ Max 1000 Unit MHz dB dB dB dB ps dB 1/V MHz dBc dBc ns ns
RF OUTPUT STAGE Output Return Loss f = 880 MHz Gain Output Noise Floor Output IP3 ACPR Output 1 dB Compression Point POWER SUPPLY Positive Supply Voltage Total Supply Current OUTPUT DISABLE Disable Threshold Maximum Attenuation Enable Response Time Disable Response Time
7.5 -2 -149 -147 24 62 11 5 130 2.5 40 15 10 5.25 150
dB dB dBm/Hz dBm/Hz dBm dBc dBm V mA V dB ns ns
Rev. 0 | Page 3 of 20
AD8340 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameters Supply Voltage VPRF, VPS2 DSOP IBBP, IBBM, QBBP, QBBM RFOP, RFOM RF Input Power at Maximum Gain (RFIP or RFIM, Single-Ended Drive) Equivalent Voltage Internal Power Dissipation JA (With Pad Soldered to Board) Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature Range (Soldering 60 sec) Rating 5.5 V 5.5 V 2.5 V 5.5V 13 dBm, re: 50 2.8 V p-p 825 mW 59 C/W 125C -40C to +85C -65C to +150C 300C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 4 of 20
AD8340 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
24 VPRF 23 CMRF 22 RFIP 21 RFIM 20 CMRF 19 VPRF
QFLP QFLM QBBP QBBM VPS2 VPS2
1 2 3 4 5 6
PIN 1 INDICATOR
AD8340
TOP VIEW (Not to Scale)
18 IFLP 17 IFLM 16 IBBP 15 IBBM 14 VPS2 13 DSOP
CMOP 7 CMOP 8 RFOP 9 RFOM 10 CMOP 11 CMOP 12
Figure 2. 24-Lead Lead Frame Chip Scale Package (LFCSP)
Table 3. Pin Function Descriptions
Pin No. 1, 2 3, 4 5, 6, 14, 19, 24 7, 8, 11, 12, 20, 23 9, 10 13 15, 16 17, 18 21, 22 Mnemonic QFLP, QFLM QBBP, QBBM VPS2, VPRF CMOP, CMRF RFOP, RFOM DSOP IBBM, IBBP IFLM, IFLP RFIM, RFIP Function Q Baseband Input Filter Pins. Connect optional capacitor to reduce Q baseband channel low-pass corner frequency. Q Channel Differential Baseband Inputs. Positive Supply Voltage. 4.75 V - 5.25 V. Device Common. Connect via lowest possible impedance to external circuit common. Differential RF Outputs. Must be ac-coupled. Differential impedance 50 nominal. Output disable. Pull high to disable output stage. I Channel Differential Baseband Inputs. I Baseband Input Filter Pins. Connect optional capacitor to reduce I baseband channel low-pass corner frequency. Differential RF Inputs. Must be ac-coupled. Differential impedance 50 nominal.
Rev. 0 | Page 5 of 20
04699-0-002
AD8340 TYPICAL PERFORMANCE CHARACTERISTICS
0 -5 PHASE SETPOINT = 90 -10 -15 PHASE SETPOINT = 270 -20 -25 -30
04699-0-003
PHASE SETPOINT = 0
GAIN CONFORMANCE ERROR (dB)
0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4
04699-0-006
GAIN SETPOINT = 1.0
GAIN (dB)
GAIN SETPOINT = 0.5
-1.6 -1.8 -2.0 0
GAIN SETPOINT = 0.1
-35 PHASE SETPOINT = 180 -40 0 0.1 0.2 0.3 0.4 0.5 0.6 GAIN SETPOINT 0.7 0.8 0.9
1.0
45
90
135
180
225
270
315
360
PHASE SETPOINT (Degrees)
Figure 3. Gain Magnitude vs. Gain Setpoint at Different Phase Setpoints, RF Frequency = 880 MHz
4 3
GAIN CONFORMANCE ERROR (dB)
Figure 6. Gain Conformance Error vs. Phase Setpoint at Different Gain Setpoints
360 330 300 270 GAIN SETPOINT = 1.0
PHASE SETPOINT = 135 PHASE SETPOINT = 45 PHASE SETPOINT = 90 PHASE SETPOINT = 0
2 1 0 -1 -2
PHASE (Degrees)
240 210 180 150 120 90 GAIN SETPOINT = 0.1 GAIN SETPOINT = 0.5
PHASE SETPOINT = 315 PHASE SETPOINT = 270
-3 -4 -5 -6 -7 0 0.1 0.2 0.3 0.4 0.5 0.6 GAIN SETPOINT 0.7 0.8 0.9 PHASE SETPOINT = 225
04699-0-004
PHASE SETPOINT = 180
30 0 0 30 60
1.0
90 120 150 180 210 240 270 300 330 360 PHASE SETPOINT (Degrees)
Figure 4. Gain Conformance Error vs. Gain Setpoint at Different Phase Setpoints
0 -2 -4 -6 -8 GAIN SETPOINT = 1.0
6 4 2 0 -2 -4
Figure 7. Phase vs. Phase Setpoint at Different Gain Setpoints
GAIN SETPOINT = 0.1
GAIN (dB)
-10 -12 -14 -16 -18
GAIN SETPOINT = 0.5
PHASE ERROR (Degrees)
GAIN SETPOINT = 1.0 GAIN SETPOINT = 0.5
-6 -8
04699-0-005
-22 -24 0 45 90 135 180 225 270 315 PHASE SETPOINT (Degrees)
-10 -12 0 45 90 135 180 225 270 PHASE SETPOINT (Degrees) 315
360
360
Figure 5. Gain Magnitude vs. Phase Setpoint at Different Gain Setpoints
Figure 8. Phase Error vs. Phase Setpoint at Different Gain Setpoints
Rev. 0 | Page 6 of 20
04699-0-008
-20
GAIN SETPOINT = 0.1
04699-0-007
60
AD8340
-142 -143 -144
0
-0.5
GAIN FLATNESS (dB)
NOISE FLOOR (dBm/Hz)
-145 RF PIN = +5dBm -146 -147 -148 -149 -150 -151 -152 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 GAIN SETPOINT
04699-0-009
-1.0
RF PIN = -5dBm RF PIN = 0dBm
-1.5
-2.0
04699-0-012
NO RF INPUT
1.0
-2.5 700
750
800 850 900 FREQUENCY (MHz)
950
1000
Figure 9. Output Noise Floor vs. Gain, Noise in dBm/Hz, No Carrier, With Carrier (20 MHz Offset) Pin = -5, 0, and +5 dBm
0 -2 GAIN SETPOINT = 1.0 -4 -6 -8
GAIN (dB)
Figure 12. Gain Flatness vs. Frequency, Maximum Gain, Phase Setpoint = 0
0
RF OUTPUT AM SIDEBAND POWER (dBm)
-10 -20 -30 -40 -50 -60 -70 -80 -90 -100 100 THIRD BASEBAND HARMONIC PRODUCT, 877MHz, 883MHz
04699-0-013
FUNDAMENTAL POWER, 879MHz, 881MHz
GAIN SETPOINT = 0.5 -10 -12 -14 -16 -18
04699-0-010
SECOND BASEBAND HARMONIC PRODUCT, 878MHz, 882MHz
-20 -22 -24 700 750
GAIN SETPOINT = 0.1
800
850
900
950
1000
200
300
400
500
600
700
800
900
1000
FREQUENCY (MHz)
DIFFERENTIAL BASEBAND INPUT LEVEL (mV p-p) (I OR Q CHANNEL DRIVEN AT 1MHz)
Figure 10. Gain vs. Frequency at Different Gain Setpoints (700 MHz to 1000 MHz), Phase Setpoint = 0
-145 -146
Figure 13. Baseband Harmonic Distortion (I and Q Channel, RF Input = 0 dBm, Balun and Cable Losses of Approximately 2 dB Not Accounted for in Plot)
14 TEMP = +25C TEMP = -40C 12
-147
NOISE (dBm/Hz)
OP1dB (dBm)
10 8 6 4 TEMP = +85C
-148 -149 -150
04699-0-011
-152 700
750
800 850 900 RF FREQUENCY (MHz)
950
1000
0 700
750
800 850 900 FREQUENCY (MHz)
950
1000
Figure 11. Output Noise Floor vs. Frequency, Maximum Gain, No RF Carrier, Phase Setpoint = 0
Figure 14. Output 1dB Compression Point vs. Frequency and Temperature, Maximum Gain, Phase Setpoint = 0
Rev. 0 | Page 7 of 20
04699-0-014
-151
2
AD8340
30 28 TEMP = -40C 26 24
30
25
GAIN SETPOINT = 1.0
20
TEMP = +85C TEMP = +25C
GAIN SETPOINT = 0.5
OIP3 (dBm)
22 20 18 16 14 12 10 700
04699-0-015
OIP3 (dBm)
15
10 GAIN SETPOINT = 0.1
04699-0-018
5
0 0 45 90 135 180 225 270 PHASE SETPOINT (Degrees) 315
750
800 850 900 FREQUENCY (MHz)
950
1000
360
Figure 15. Output IP3 vs. Frequency and Temperature, Maximum Gain, I Only
0
Figure 18. Output IP3 vs. Gain and Phase Setpoints, 2.5 MHz Carrier Spacing
REF LVL 0 dBm RBW 30kHz VBW 30kHz SWT 100ms RF ATT 20dB MIXER -10dBm UNIT dBm
A
RF OUTPUT AM SIDEBAND POWER (dBm)
-5 1V p-p BB INPUT -10
0 -10
SECOND BASEBAND HARMONIC
500mV p-p BB INPUT -15
-30 -40 -50 -60 -70 -80 -90
SECOND BASEBAND HARMONIC
-20
OUTPUT POWER (dBm)
1 RM
-20
200mV p-p BB INPUT -30 0 50 100 150 200 250 FREQUENCY (MHz) 300 350
04699-0-016
-25
UNDESIRED SIDEBAND
DESIRED SIDEBAND
RF FEEDTHROUGH
400
-100
Figure 16. I/Q Modulation Bandwidth vs. Baseband Magnitude
CENTER 880 MHz
500 kHz/ FREQUENCY (MHz)
SPAN 5 MHz
Figure 19. Single-Sideband Performance, 880 MHz, -10 dBm RF Input; 1 MHz, 500 mV p-p Differential BB Drive
14 12 10 8 6
OP1dB (dBm)
90
GAIN SETPOINT = 1.0
120
60
GAIN SETPOINT = 0.5
4 2 0 -2 -4 -6
04699-0-017
150
30
180
1.5GHz 500MHz 1.5GHz
0
-8 -10 -12 0 45 90
GAIN SETPOINT = 0.1
210 500MHz 240 270 IMPEDANCE CIRCLE S11 RF PORT WITH 5.6nH INDUCTORS S11 RF PORT WITHOUT INDUCTORS 300
330
225 180 270 135 PHASE SETPOINT (Degrees)
315
360
Figure 17. Output 1dB Compression Point vs. Gain and Phase Setpoints
Figure 20. Input and Output Impedance Smith Chart (with Frequency Markers)
Rev. 0 | Page 8 of 20
04699-0-020
04699-0-019
AD8340
90 120 60
0 -5 -10
RF OUTPUT POWER (dBm)
-15 -20 -25 -30 -35 -40 -45 -50 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 DSOP VOLTAGE (V) 4.0 4.5
04699-0-024
150
1.5GHz
500MHz
30
180 500MHz 1.5GHz 210
0
330
5.0
240 270
300
IMPEDANCE CIRCLE S22 PORT WITH 1 TO 1 TRANSFORMER SDD22 PORT DIFFERENTIAL
Figure 21. Output Impedance Smith Chart (with Frequency Markers)
6 4 2 PHASE SETPOINT = 45 PHASE SETPOINT = 0 0
04699-0-021
Figure 24. Power Shutdown Attenuation
TEK FAST ACQ SAMPLE
PHASE ERROR (Degrees)
2V/DIV
-4 -6 -8 PHASE SETPOINT = 90 -10
04699-0-022
CHAN 1/3 (V)
-2
200mV/DIV 3
DSOP
-12 -14 0 0.1 0.2 0.3 0.4 0.5 0.6 GAIN SETPOINT 0.7 0.8 0.9
1.0
CH1 200mV CH3 2.0V
M 10.0ns 5.0GS/s A CH2 160mV TIME (10ns/DIV)
ET 200ps/pt 74.0ns
Figure 22. Phase Error vs. Gain Setpoint by Phase Setpoint, 5 V dc, 25C, 880 MHz
Figure 25. Power Shutdown Response Time
135 134 133
SUPPLY CURRENT (mA)
132 5.25V 131 130 129 128 127 126 125 -40 -30 -20 -10 4.75V
04699-0-023
5V
0
10
20
30
40
50
60
70
80
TEMPERATURE (C)
Figure 23. Supply Current vs. Temperature
Rev. 0 | Page 9 of 20
04699-0-025
RF OUTPUT
AD8340 THEORY OF OPERATION
The AD8340 is a linear RF vector modulator with Cartesian baseband controls. In the simplified block diagram given in Figure 26, the RF signal propagates from the left to the right while baseband controls are placed above and below. The RF input is first split into in-phase (I) and quadrature (Q) components. The variable attenuators independently scale the I and Q components of the RF input. The attenuator outputs are then summed and buffered to the output. By controlling the relative amounts of I and Q components that are summed, continuous magnitude and phase control of the gain is possible. Consider the vector gain representation of the AD8340 expressed in polar form in Figure 27. The attenuation factors for the I and Q signal components are represented on the x- and y-axis, respectively, by the baseband inputs, VBBI and VBBQ. The resultant of their vector sum represents the vector gain, which can also be expressed as a magnitude and phase. By applying different combinations of baseband inputs, any vector gain within the unit circle can be programmed. A change in sign of VBBI or VBBQ can be viewed as a change in sign of the gain or as a 180 phase change. The outermost circle represents the maximum gain magnitude of unity. The circle origin implies, in theory, a gain of 0. In practice, circuit mismatches and unavoidable signal feedthrough limit the minimum gain to approximately -40 dB. The phase angle between the resultant gain vector and the positive x-axis is defined as the phase shift. Note that there is a nominal, systematic insertion phase through the AD8340 to which the phase shift is added. In the following discussions, the systematic insertion phase is normalized to 0. The correspondence between the desired gain and phase setpoints, GainSP and PhaseSP, and the Cartesian inputs, VBBI and VBBQ, is given by simple trigonometric identities
Pure amplitude modulation is represented by radial movement of the gain vector tip at a fixed angle, while pure phase modulation is represented by rotation of the tip around the circle at a fixed radius. Unlike traditional I-Q modulators, the AD8340 is designed to have a linear RF signal path from input to output. Traditional I-Q modulators provide a limited LO carrier path through which any amplitude information is removed.
VBBI I CHANNEL INPUT LINEAR ATTENUATOR V-I SINGLE-ENDED OR DIFFERENTIAL 50 INPUT Z 0/90 V-I LINEAR ATTENUATOR Q CHANNEL INPUT VBBQ OUTPUT DISABLE
04699-0-026
I-V
SINGLE-ENDED OR DIFFERENTIAL 50 OUTPUT
Figure 26. Simplified Architecture of the AD8340
Vq MAX GAIN = 0dB +0.5
A |A|
-0.5 +0.5
Vi
-0.5
Figure 27. Vector Gain Representation
RF QUADRATURE GENERATOR
The RF input is directly coupled differentially or single-ended to the quadrature generator, which consists of a multistage RC polyphase network tuned over the operating frequency range of 700 MHz to 1000 MHz. The recycling nature of the polyphase network generates two replicas of the input signal, which are in precise quadrature, i.e., 90, to each other. Since the passive network is perfectly linear, the amplitude and phase information contained in the RF input is transmitted faithfully to both channels. The quadrature outputs are then separately buffered to drive the respective attenuators. The characteristic impedance of the polyphase network is used to set the input impedance to the AD8340.
GainSP =
[(V
BBI
/ VO )2 + (VBBQ /VO )2
]
PhaseSP = arctan(VBBQ /VBBI ) where: VO is the baseband scaling constant (500 mV). VBBI and VBBQ are the differential I and Q baseband voltages, respectively. Note that when evaluating the arctangent function, the proper phase quadrant must be selected. For example, if the principal value of the arctangent (known as the Arctangent(x)) is used, quadrants 2 and 3 would be interpreted mistakenly as quadrants 4 and 1, respectively. In general, both VBBI and VBBQ are needed in concert to modulate the gain and the phase.
Rev. 0 | Page 10 of 20
04699-0-027
MIN GAIN < -30dB
AD8340
I-Q ATTENUATORS AND BASEBAND AMPLIFIERS
The proprietary linear-responding attenuator structure is an active solution with differential inputs and outputs that offer excellent linearity, low noise, and greater immunity from mismatches than other variable attenuator methods. The gain, in linear terms, of the I and Q channels is proportional to its control voltage with a scaling factor designed to be 2/V, i.e., a full-scale gain setpoint of 1.0 (-2 dB) for VBBI (Q) of 500 mV. The control voltages can be driven differentially or single-ended. The combination of the baseband amplifiers and attenuators allows for maximum modulation bandwidths in excess of 200 MHz.
GAIN AND PHASE ACCURACY
There are numerous ways to express the accuracy of the AD8340. Ideally, the gain and phase should precisely follow the setpoints. Figure 3 illustrates the gain error in dB from a best fit line, normalized to the gain measured at the gain setpoint = 1.0, for the different phase setpoints. Figure 6 shows the gain error in a different form; the phase setpoint is swept from 0 to 360 for different gain setpoints. Figure 8 and Figure 22 show analogous errors for the phase error as a function of gain and phase setpoints. The accuracy clearly depends on the region of operation within the vector gain unit circle. Operation very close to the origin generally results in larger errors as the relative accuracy of the I and Q vectors degrades.
OUTPUT AMPLIFIER
The output amplifier accepts the sum of the attenuator outputs and delivers a differential output signal into the external load. The output pins must be pulled up to an external supply, preferably through RF chokes. When the 50 load is taken differentially, an output P1dB and IP3 of 11 dBm and 24 dBm is achieved, respectively, at 880 MHz. The output can be taken in single-ended fashion, albeit at lower performance levels.
RF FREQUENCY RANGE
The frequency range on the RF input is limited by the internal polyphase quadrature phase-splitter. The phase-splitter splits the incoming RF input into two signals, 90 out of phase, as previously described in the RF Quadrature Generator section. This polyphase network has been designed to ensure robust quadrature accuracy over standard fabrication process parameter variations for the 700 MHz to 1 GHz specified RF frequency range. Using the AD8340 as a single-sideband modulator and measuring the resulting sideband suppression is a good gauge of how the quadrature accuracy is maintained over RF frequency. A typical plot of sideband suppression from 500 MHz to 1.5 GHz is shown in Figure 28. The level of sideband suppression degradation outside the 700 MHz to 1 GHz specified range will be subject to manufacturing process variations.
0
NOISE AND DISTORTION
The output noise floor and distortion levels vary with the gain magnitude but do not vary significantly with the phase. At the higher gain magnitude setpoints, the OIP3 and the noise floor vary in direct proportion with the gain. At lower gain magnitude setpoints, the noise floor levels off while the OIP3 continues to vary with the gain.
-5
SB SUPPRESSION (dBc)
-10 -15
-20 -25
-35 500
600
700
800
900
1000 1100 1200 1300 1400 1500
FREQUENCY (MHz)
Figure 28. Sideband Suppression vs. Frequency
Rev. 0 | Page 11 of 20
04699-0-028
-30
AD8340 APPLICATIONS
USING THE AD8340
The AD8340 is designed to operate in a 50 impedance system. Figure 30 illustrates an example where the RF input is driven in a single-ended fashion while the differential RF output is converted to a single-ended output with a RF balun. The baseband controls for the I and Q channels are typically driven from differential DAC outputs. The power supplies, VPRF and VPS2, should be bypassed appropriately with 0.1 F and 100 pF capacitors. Low inductance grounding of the CMOP and CMRF common pins is essential to prevent unintentional peaking of the gain. loss of >10 dB over the operating frequency range. Different matching inductors can improve matching over a narrower frequency range. The single-ended and differential input impedances are exactly the same.
100pF 5.6nH RFIM ~1VDC 100pF 5.6nH RFIP 50
04699-0-029
RC PHASE
RF
Figure 29. RF Input Interface to the AD8340 Showing Coupling Capacitors and Matching Inductors
RF INPUT AND MATCHING
The input impedance of the AD8340 is defined by the characteristics of the polyphase network. The capacitive component of the network causes its impedance to roll-off with frequency albeit at a slower rate than 6 dB/octave. By using matching inductors on the order of 5.6 nH in series with each of the RF inputs, RFIP and RFIM, a 50 match is achieved with a return
The RFIP and RFIM should be ac-coupled through low loss series capacitors as shown in Figure 29. The internal dc levels are at approximately 1 V. For single-ended operation, one input is driven by the RF signal while the other input is ac grounded.
VP
C2 100pF IBBM IBBP C12 (SEE TEXT) C8 0.1F VP C6 100pF L3 5.6nH C7 100pF
C1 0.1F VP
A B
OUTPUT DISABLE
IFLP VPRF CMRF RFIM
VPS2
IBBP
IFLM
IBBM
DSOP CMOP CMOP RFOM C17 100pF
ETC1-1-13
RF INPUT
AD8340
C5 100pF L4 5.6nH RFIP CMRF
QBBM QBBP QFLM
RF OUTPUT
RFOP CMOP
VPS2
L1 120nH
C18 L2 100pF 120nH C14 0.1F VP
VP C3 0.1F C4 100pF
VPRF
QFLP
CMOP VPS2
QBBP QBBM C9 100pF
Figure 30. Basic Connections
Rev. 0 | Page 12 of 20
04699-0-030
C11 (SEE TEXT)
C10 0.1F
AD8340
RF OUTPUT AND MATCHING
The RF outputs of the AD8340, RFOP and RFOM, are open collectors of a transimpedance amplifier which need to be pulled up to the positive supply, preferably with RF chokes as shown in Figure 31. The nominal output impedance looking into each individual output pin is 25 . Consequently, the differential output impedance is 50 .
VP
-0.5 -1.0 -1.5 -2.0 -2.5 RL2 = SHORT
GAIN (dB)
-3.0 -3.5 -4.0 -4.5
RL2 = 50
RT RFOM ISIG GM RFOP RT
120nH 100pF 1:1 100pF 50 DIFFERENTIAL RF OUTPUT
-5.5 -6.0 700
RL2 = OPEN 800 900 FREQUENCY (MHz)
1000
04699-0-031
Figure 32. Gain of the AD8340 Using a Single-Ended Output with Different Dummy Loads, RL2 on the Unused Output
Figure 31. RF Output Interface to the AD8340 Showing Coupling Capacitors, Pull-Up RF Chokes, and Balun
Since the output dc levels are at the positive supply, ac coupling capacitors will usually be needed between the AD8340 outputs and the next stage in the system. A 1:1 RF broadband output balun, such as the ETC1-1-13 (M/A-COM), converts the differential output of the AD8340 into a single-ended signal. Note that the loss and balance of the balun directly impact the apparent output power, noise floor, and gain/phase errors of the AD8340. In critical applications, narrow-band baluns with low loss and superior balance are recommended. If the output is taken in a single-ended fashion directly into a 50 load through a coupling capacitor, there will be an impedance mismatch. This can be resolved with a 1:2 balun to convert the single-ended 25 output impedance to 50 . If loss of signal swing is not critical, a 25 back termination in series with the output pin can also be used. The unused output pin must still be pulled up to the positive supply. The user may load it through a coupling capacitor with a dummy load to preserve balance. The gain of the AD8340 when the output is singleended varies slightly with dummy load value as shown in Figure 32.
The RF output signal can be disabled by raising the DSOP pin to the positive supply. The shutdown function provides >40 dB attenuation of the input signal even at full gain. The interface to DSOP is high impedance and the shutdown and turn-on response times are <100 ns. If the disable function is not needed, the DSOP should be tied to ground.
DRIVING THE I-Q BASEBAND CONTROLS
The I and Q inputs to the AD8340 set the gain and phase between input and output. These inputs are differential and should normally have a common-mode level of 0.5 V. However, when differentially driven, the common mode can vary from 250 mV to 750 mV while still allowing full gain control. Each input pair has a nominal input swing of 0.5 V differential around the common-mode level. The maximum gain of unity is achieved if the differential voltage is equal to +500 mV or -500 mV. So with a common-mode level of 500 mV, IBBP and IBBM will each swing between 250 mV and 750 mV. The I and Q inputs can also be driven with a single-ended signal. In this case, one side of each input should be tied to a low noise 0.5 V voltage source (a 0.1 F decoupling capacitor located close to the pin is recommended), while the other input swings from 0 V to 1 V. Differential drive generally offers superior even-order distortion and lower noise than single-ended drive. The bandwidth of the baseband controls exceeds 200 MHz even at full-scale baseband drive. This allows for very fast gain and phase modulation of the RF input signal. In cases where lower modulation bandwidths are acceptable or desired, external filter capacitors can be connected across Pins IFLP to IFLM and QFLP to QFLM to reduce the ingress of baseband noise and spurious signal into the control path.
Rev. 0 | Page 13 of 20
04699-0-032
-5.0
AD8340
DIFFERENTIAL PEAK-TO-PEAK SWING (R3)
The 3 dB bandwidth is set by choosing CFLT according to the following equation:
f3dB
45 kHz x 10 nF C external + 0.5 pF
This equation has been verified for values of CFLT from 10 pF to 0.1 F (bandwidth settings of approximately 4.5 kHz to 43 MHz).
INTERFACING TO HIGH SPEED DACs
The AD977x family of dual DACs is well suited to driving the I and Q vector controls of the AD8340. While these inputs can in general be driven by any DAC, the differential outputs and bias level of the ADI TxDAC(R) family allows for a direct connection between DAC and modulator. The AD977x family of dual DACs have differential current outputs. The full-scale current is user programmable and is usually set to 20 mA, that is, each output swings from 0 mA to 20 mA. The basic interface between the AD9777 DAC outputs and the AD8340 I and Q inputs is shown in Figure 33. The Resistors R1 and R2 set the dc bias level according to the equation: Bias Level = Average Output Current x R1 For example, if the full-scale current from each output is 20 mA, each output will have an average current of 10 mA. Therefore to set the bias level to the recommended 0.5 V, R1 and R2 should be set to 50 each. R1 and R2 should always be equal. If R3 is omitted, this will result in an available swing from the DAC of 2 V p-p differential, which is twice the maximum voltage range required by the AD8340. DAC resolution can be maximized by adding R3, which scales down this voltage according to the following equation: Full Scale Swing = R2 2 x I MAX (R1 || (R2 + R3)) x 1 - R2 + R3
AD9777
IOUTA1 R1 R2 IOUTB1 OPTIONAL LOW-PASS FILTER R3 IBBM
1.15 1.13 1.10 1.08 1.05 1.02 1.00 0.97 0.95 0.92 0.90 0.88 0.85 0.82 0.80 0.77 0.75 0.72 0.70 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 130 R3
Figure 34. Peak-to-Peak DAC Output Swing vs. Swing Scaling Resistor R3 (R1 = R2 = 50 )
Figure 34 shows the relationship between the value of R3 and the peak baseband voltage with R1 and R2 equal to 50 . From Figure 34, it can be seen that a value of 100 for R3 will provide a peak-to-peak swing of 1 V p-p differential into the AD8340's I and Q inputs. When using a DAC, low-pass image reject filters are typically used to eliminate the Nyquist images produced by the DAC. They also provide the added benefit of eliminating broadband noise that might feed into the modulator from the DAC.
CDMA2000 APPLICATION
To test the compliance to the CDMA2000 base station standard, a single-carrier CDMA2000 test model signal (forward pilot, sync, paging, and six traffic as per 3GPP2 C.S0010-B, Table 6.5.2.1) was applied to the AD8340. A cavity tuned filter was used to reduce noise from the signal source being applied to the device. The 4.6 MHz pass band of this filter is apparent in the subsequent spectral plots. Figure 35 shows a plot of the spectrum of the output signal under nominal conditions. POUT is equal to -5 dBm and VI = VQ = 0.353 V, i.e., VIBBP - VIBBM = VQBBP - VQBBM = 0.353 V. Adjacent channel power is measured in 30 kHz resolution bandwidth at 750 KHz and 1.98 MHz carrier offset. Noise floor is measured at 4 MHz carrier offset.
AD8340
IBBP
IOUTA2 R1 R2 IOUTB2 OPTIONAL LOW-PASS FILTER R3
QBBP
Figure 33. Basic AD9777 to AD8340 Interface
Rev. 0 | Page 14 of 20
04699-0-033
QBBM
04699-0-034
AD8340
BS, 1X, C0 : ADJ CHANNEL REF -12dBm OFFSET 0.5 dB -20 -30 -40 -50 -60 SWP 50 OF 50 -70 -80 -90 -100 -110 CENTER 880MHz 1MHz/ SPAN 10MHz 2 1
04699-0-035
*ATT 5dB
*RBW 30kHz *VBW 30kHz *SWT 100ms
MARKER 2 [T1 NOI] -148.76dBm/Hz 876.009615385MHz CH PWR ACP LOW ACP UP ALT1 LOW ALT1 UP -5.17dBm -60.94dB -60.08dB -86.40dB -86.80dB LVL NOR
10 0 -10 -20 -30 -40 ACP - 1.98MHz OFFSET, 30kHz RBW -50 -60 -70 NOISE - 4MHz OFFSET, 1MHz RBW ACP - 750kHz OFFSET, 30kHz RBW POUT vs. VIN
-50 -55 -60 -65 -70 -75 -80 -85 -90 500
MARKER 1 [T1 NOI] -148.89dBm/Hz 884.006410256MHz
ACP - dBc (30kHz RBW) NOISE - 4MHz CARRIER OFFSET - dBm (1MHz RBW)
04699-0-038
OUTPUT POWER (dBm)
0
50
100
150
200 250 300 VI = VQ =VIN (mV)
350
400
450
Figure 35. Output Spectrum, Single-Carrier CDMA2000 Test Model at -5 dBm, VI = VQ = 0.353 V, ACP Measured at 750 kHz and 1.98 KHz Carrier Offset, Noise Measured at 4 MHz Carrier Offset, Input Signal Filtered Using a Cavity Tuned Filter (Pass Band = 4.6 MHz)
Figure 37. Output Power, Noise, and ACP vs. I and Q Control Voltages, CDMA2000 Test Model, VI = VQ, ACP Measured in 30 kHz RBW at 750 kHz and 1.98 kHz Carrier Offset, Noise Measured at 4 MHz Carrier Offset
Holding the I and Q control voltages steady at 0.353 V, input power was swept. Figure 36 shows the resulting output power, noise floor, and adjacent channel power ratio. Noise floor is presented as noise in a 1 MHz bandwidth as defined by the 3GPP2 specification.
-30 -30
NOISE - dBm @ 4MHz CARRIER OFFSET (1MHz RBW)
In contrast to Figure 36, Figure 37 shows that for a fixed input power, ACP remains fairly constant as gain and phase are changed (this is not true for very high input powers). The noise floor still drops with decreasing gain, but it never reaches the -90 dBm level in Figure 37. Figure 38 shows the output spectrum for a 3-carrier CDMA2000 spectrum. Again, the signal being applied to the AD8340 is filtered by a cavity-tuned filter with a -3 dB bandwidth of 4.6 MHz. To reduce distortion, the total output carrier power has been reduced to approximately -8 dBm (per-carrier power = -12.6 dBm). Adjacent channel power ratios of -61 dBc (2 MHz from center of spectrum) and -82 dBc (3.23 MHz from center of spectrum) were measured. The noise floor, measured at 5.25 MHz carrier offset, is approximately -149 dBm/Hz (-89 dBm in a 1 MHz bandwidth). So while some dynamic range has been lost due to output power back-off, ACP stays approximately equal and noise floor improves slightly.
REF -15 dBm -20 -30 -40 OFFSET 0.5dB *ATT 5dB *RBW 30kHz *VBW 300kHz *SWT 5s MARKER 1 [T1 NOI] -148.83dBm/Hz 885.252403846MHz CH1 CH2 CH3 TOTAL ACP LOW ACP UP ALT1 LOW ALT1 UP -12.65dBm -12.58dB A -12.87dB SOL -7.93dB -61.41dB -61.87dB LVL -82.36dB -81.92dB NOR
-40
ACP - dBc (30kHz RBW)
-40
-50 -60 ACP - 750kHz OFFSET, 30kHz RBW -70 -80 ACP - 1.98MHz OFFSET, 30kHz RBW
-50
-60
-70 -80 -90 NOISE - 4MHz OFFSET, 1MHz RBW
-100 -30
-25
-20
-15 -10 -5 OUTPUT POWER (dBm)
0
5
-100
Figure 36. Noise and ACP vs. Output Power, Single-Carrier CDMA2000 Test Model, VI = VQ = 0.353, ACP Measured in 30 kHz RBW at 750 kHz and 1.98 KHz Carrier Offset, Noise Measured at 4 MHz Carrier Offset
The results show that at an output power of +3 dBm, ACP is still in compliance with the standard (<-45 dBc @ 750 MHz and <-60 dBc @ 1.98 MHz). At low output power levels, ACP at 1.98 MHz carrier offset degrades as the noise floor of the AD8340 becomes the dominant contributor to measured ACP. Measured noise at 4 MHz carrier offset begins to increase sharply above 0 dBm output power. This increase is not due to noise but results from increased carrier-induced distortion. As output power drops below 0 dBm, the noise floor drops towards -90 dBm. With a fixed input power of 2.4 dBm, the output power was again swept by exercising the I and Q inputs. VI and VQ were kept equal and were swept from 10 mV to 500 mV. The resulting output power, ACP, and noise floor are shown in Figure 37.
04699-0-036
-90
-50 -60 -70 -80 -90 -100 -110 CENTER 880MHz 1.5MHz/
1
SPAN 15MHz
Figure 38. Output Spectrum, 3-Carrier CDMA2000 Test Model at -12.5 dBm/Carrier, VI = VQ = 0.353 V, ACP Measured at 2 MHz and 3.23 KHz Offset from Center of Spectrum, Noise Measured at 5.25 MHz Carrier Offset, Input Signal Filtered Using a Cavity Tuned Filter (Pass Band = 4.6 MHz)
Rev. 0 | Page 15 of 20
04699-0-037
AD8340 EVALUATION BOARD
The evaluation board circuit schematic for the AD8340 is shown in Figure 39. The evaluation board is configured to be driven from a single-ended 50 source. Although the input of the AD8340 is differential, it may be driven single-ended, with no loss of performance. The low-pass corner frequency of the baseband I and Q channels can be reduced by installing capacitors in the C11 and C12 positions. The low-pass corner frequency for either channel is approximated by f 3dB 45 kHz x 10 nF C external + 0.5 pF The baseband input of the AD8340 requires a differential voltage drive. The evaluation board is set up to allow such a drive by connecting the differential voltage source to QBBP and QBBM. The common-mode voltage should be maintained at approximately 0.5 V. For this configuration, Jumpers W1 to W4 should be removed. The baseband input of the evaluation board may also be driven with a single-ended voltage. In this case, a bias level is provided to the unused input from Potentiometer R10 by installing either W1 or W2. Setting SW1 in Position B disables the AD8340 output amplifier. With SW1 set to Position A, the output amplifier is enabled. With SW1 set to Position A, an external voltage signal, such as a pulse, can be applied to the DSOP SMA connector to exercise the output amplifier enable/disable function.
On this evaluation board, the I and Q baseband circuits are identical to each other, so the following description applies equally to each. The connections and circuit configuration for the Q baseband inputs are described in Table 4.
Rev. 0 | Page 16 of 20
AD8340
Table 4. Evaluation Board Configuration Options
Components R7, R9, R11, R14, R15, R19, R20, R21, C15, C19, W3, W4 Function I Channel Baseband Interface. Resistors R7 and R9 may be installed to accommodate a baseband source that requires a specific terminating impedance. Capacitors C15 and C19 are bypass capacitors. For single-ended baseband drive, the Potentiometer R11 can be used to provide a bias level to the unused input (install either W3 or W4). Default Conditions R7, R9 = Not Installed R11 = Potentiometer, 2 k, 10 Turn (Bourns) R14 = 4 k (Size 0603) R15 = 44 k (Size 0603) R19, R20, R21 = 0 (Size 0603) C15, C19 = 0.1 F (Size 0603) W3 = Jumper (Installed) W4 = Jumper (Open) R1, R3 = Not Installed R10 = Potentiometer, 2 k, 10 Turn (Bourns) R12 = 4 k (Size 0603) R13 = 44 k (Size 0603) R16, R17, R18 = 0 (Size 0603) C16, C20 = 0.1 F (Size 0603) W1 = Jumper (Installed) W2 = Jumper (Open) C11, C12 = Not Installed
R1, R3, R10, R12, R13, R16, R17, R18, C16, C20, W1, W2
Q Channel Baseband Interface. See the I Channel Baseband Interface section.
C11, C12
T1, C17, C18, L1, L2
Baseband Low-Pass Filtering. By adding Capacitor C11 between QFLP and QFLM, and C12 between IFLP and IFLM, the 3 dB low-pass corner frequency of the baseband interface can be reduced from 230 MHz (nominal). See equation in text. Output Interface. The 1:1 balun transformer, T1, converts the 50 differential output to 50 single-ended. C17 and C18 are dc blocks. L1 and L2 provide dc bias for the output.
L3, L4, C5, C6
C2, C4, C7, C9, C14, C1, C3, C8, C10, R2, R4, R5, R6
Input Interface. The input impedance of the AD8340 requires 5.6 nH inductors in series with RFIP and RFIM for optimum return loss when driven by a single-ended 50 line. C5 and C6 are dc blocks. Supply Decoupling.
C17, C18 = 100 pF (Size 0603) T1 = ETC1-1-13 (M/A-COM) L1, L2 = 120 nH (Size 0603) L3, L4 = 5.6 nH (Size 0402) C5, C6 = 100 pF (Size 0603) C2, C4, C7, C9, C14 = Open (Size 0603) C1, C3, C8, C10 = 0.1 F (Size 0603) R2, R4, R5, R6 = 0 (Size 0603) R8 = 10 k (Size 0603) SW1 = SPDT (Position A, Output Enabled)
R8, SW1
Output Disable Interface. The output stage of the AD8340 is disabled by applying a high voltage to the DSOP pin by moving SW1 to Position B. The output stage is enabled moving SW1 to Position A. The output disable function can also be exercised by applying an external high or low voltage to the DSOP SMA connector with SW1 in Position A.
Rev. 0 | Page 17 of 20
AD8340
IBBP IBBM
R9 (OPEN)
C19 R7 0.1F (OPEN) R19 0 W3 R20 0
VP TEST POINT
GND TEST POINT
W4 R21 0 C15 0.1F
C2 (OPEN)
VS R14 4k R11 2k R15 44k
R2 0
C1 0.1F C12 (OPEN) C7 (OPEN) VP C8 0.1F R8 10k SW1 B A DSOP
IFLP VPRF CMRF RFIM
VPS2
IFLM
IBBP
IBBM
R5 0
DSOP CMOP CMOP RFOM
C6 100pF
L3 5.6nH
C17 100pF
T1 ETC1-1-13 M/A-COM RFOP
AD8340
RFIN C5 100pF VP C4 (OPEN) R4 0 C3 0.1F L4 5.6nH RFIP CMRF RFOP CMOP L1 120nH C18 L2 100pF 120nH
QBBM
QBBP
QFLM
VPRF
VPS2
CMOP VPS2 C14 0.1F VP R6 0
QFLP
C11 (OPEN)
C10 0.1F
C9 (OPEN)
R12 4k
R10 2k
R13 44k VS
C16 0.1F
W2 R17 0 R1 OPEN QBBP
W1 R16 0 R18 0
R3 C20 OPEN 0.1F QBBM
04699-0-039
Figure 39. Evaluation Board Schematic
Rev. 0 | Page 18 of 20
AD8340
04699-0-040
Figure 40. Component Side Layout
Figure 41. Component Side Silkscreen
Rev. 0 | Page 19 of 20
04699-0-041
AD8340 OUTLINE DIMENSIONS
4.00 BSC SQ 0.60 MAX 0.60 MAX
19 18 24 1
PIN 1 INDICATOR 2.25 2.10 SQ 1.95
6
PIN 1 INDICATOR
TOP VIEW
3.75 BSC SQ
0.50 BSC 0.50 0.40 0.30
BOTTOM VIEW
13 12 7
0.25 MIN 2.50 REF
1.00 0.85 0.80
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.20 REF COPLANARITY 0.08
SEATING PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2
Figure 42. 24-Lead Lead Frame Chip Scale Package [LFCSP] (CP-24) Dimensions shown in millimeters
ORDERING GUIDE
Models AD8340ACPZ-WP1, 2 AD8340ACPZ-REEL71 AD8340-EVAL Temperature Range -40C to +85C -40C to +85C Package Description 24-Lead Lead Frame Chip Scale Package (LFCSP) 24-Lead Lead Frame Chip Scale Package (LFCSP) Evaluation Board Package Option CP-24 CP-24 Order Multiple 64 1,500 1
1 2
Z = Pb-free part. WP = Waffle pack.
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04699-0-6/04(0)
Rev. 0 | Page 20 of 20

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